The present invention relates generally to a MIS transistor and a method for producing the same. More specifically, the invention relates to a MIS transistor having a large driving current and a small parasitic capacitance, and a method for producing the same.
As a request to achieve the scaling down of a transistor having the metal insulator semiconductor (MIS) structure grows more intense, the scaling down of the MIS transistor progresses steadily at present. The scaling down of the MIS transistor is carried out by using a technique called a scaling rule for forming a source/drain region in proportion to a gate length, specifically by reducing the junction depth of an impurity diffusion region, a so-called diffusion layer, which is to be a drain and/or source, as the gate length decreases when the gate length decreases.
However, in a fine transistor having a gate length of less than 0.2 .mu.m, the depth (Xj) of diffusion is too small, so that there is a problem in that the resistance of the gate increase to increase the parasitic resistance of the whole transistor to reduce a substantial driving current. In order to reduce the parasitic resistance, it is possible that the depth of the junction is reduced when the metal silicidation of the source and drain to be introduced is carried out. However, when the reduction of the depth of the junction is too great, there is a problem in that the silicide metal does not remain in the diffusion layer and penetrates the substrate to cause the junction leak.
The problem in that the resistance increases or the silicidation is difficult to carry out when the junction is shallow has been solved by the art called an elevated source/drain, a concave transistor, a recessed channel transistor or the like. This transistor has a structure wherein the surfaces of the source and drain are higher than the channel surface of the transistor (e.g., S.M. Sze Physics of Semiconductor Devices second edition, 1981, pp490). FIG. 1 shows a MIS transistor which has such a concave MOS structure and which comprises a semiconductor substrate 1, source/drain regions 2, a channel plane arranged therebetween, an SiO.sub.2 film 51 provided on the top of the channel plane 7, and a gate electrode 6 facing the channel plane via the SiO.sub.2, film 51.
In FIG. 1, each or the source/drain regions 2 include a first impurity diffusion region 2a formed in the semiconductor substrate 1 (below the channel plane 7 in the drawing), and a second impurity diffusion region 2b laminated outside of the channel plane 7 (above the channel plane 7 in the drawing). Such a structure wherein the gate electrode 6 is surrounded by the second impurity diffusion regions 2b via the SiO.sub.2 film 51 may be considered as a construction wherein a groove is formed in the source/drain regions 2 or as a construction wherein the second impurity diffusion regions 2b are elevated.
However, in the conventional MIS transistor having the structure shown in FIG. 1, the gate electrode 6 is surrounded by the source/drain diffusion layer 2 via the SiO.sub.2 (insulator) film 51, so that there is a problem in that the gate-to-drain capacitance and source-to-drain capacitance increase, so that the switching speed of the transistor deteriorates to a large extent.
As described above, in the conventional MIS transistor, there is a problem in that it is not possible to reduce both of the resistance of the source/drain diffusion layer and the gate parasitic capacitance.